Pulse reshaper employing plurality of delay line units interconnected by differential amplifier means



y 1966 FUJlO KOBAYASHI ETAL 3,254,233

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PULSE RESHAPER EMPLOYING PLURALITY OF DELAY LINE UNITS INTERCONNECTED BYDIFFERENTIAL AMPLIFIER MEANS Filed March 5, 1963 5 Sheets$heet 5 InVEnTO RS FuS-o Koba ash'. Kaname. SaKai By GALE Tn-M Qa.

m'voeney 3,254,233 PULSE RESHAPER EMPLOYING PLURALITY'OF DELAY LINEUNITS INTERCONNEUI'ED BY DIFFERENTIAL AMPLIFIER MEANS Fujio Kobayashiand Kaname Sakai, Tokyo, Japan, as-

signors to Hitachi, Ltd., Tokyo, Japan, a corporation of Japan v FiledMar. 5, 1963, Ser. No. 262,879 Claims priority, application Japan, Mar.7, 1962, 37/ 8,235 Claims. (Cl. 307-885) The present invention relatesto methods of reshaping pulses for use in pulse transmission linesincluding delay line registers and is primarily intended to overcomevarious difiiculties encountered in conventional pulsereshaping methods.

According to one aspect of the present invention, there is provided, ina pulse transmission system including a cascade connection of aplurality of current-switching amplifiers with circuit elements forpulse transmission interposed therebetween so that pulses aretransmitted through the successive stages of amplification, a method ofreshaping pulses comprising producing an inverted output at each stageof amplification and transmitting said output to the next stage ofamplilcation.

According to another aspect of the present invention, there is provideda delay line register comprising a delay line divided into a pluralityof delay line units, and a pair of current-switching amplifiersrespectively arranged on the input and output sides of each of saiddelay line units in cascade connection for transmitting the invertedoutput of each of said amplifiers to thenext stage.

The invention will now be more particularly described with reference tothe accompanying drawings, in which:

FIGS. 1 and 3 are block diagrams illustrating two respective forms ofdelay line register;

FIG. 2 graphically illustrates the characteristics of a typical delayline;

FIG. 4 is a block diagram of a conventional pulse reshaping circuit; I

- FIG. 5 illustrates a typical form of current-switching amplifierusable in pulse reshaping circuits;

FIG. 6 is a diagram showing the Waveform of a pulse signal changing withvariation in the operating voltage level while passing through the pulsereshaping circuit of FIG. 4;

FIG. 7 is a diagram similar to FIG. 6 for the pulse reshaping circuitshown in FIG. 8;

FIG. 8 is a block diagram of a pulse reshaping circuit embodying thepresent invention; and

FIG. 9 represents the results of marginal checks conducted with theconventional and inventive delay line registers.

Delay line registers as used in digital computers and the likenecessitate pulse reshaping circuits for reshaping pulse signals heavilydistorted while being transmitted through the delay line.

First, such pulse reshaping circuit will be explained for betterunderstanding of the present invention. FIG.

. 1 illustrates one conventional form of delay line register,

which includes a delay line De and pulse reshaping circuits Si, S0operable by logical gating with clock pulse e The input pulse e, isfirst retimed and reshaped by the input-side pulse reshaper Si withclock pulse e fed therein, then delayed one'or more word-times, andagain retimed and reshaped by the. output-side pulse reshaper So withclock pulse e to obtain a delayed output signal e With such delay lineregister, the waveform distortion of a pulse signal during transmissionthrough the delay line and the variation in the operating voltage levelof United States Patent 0 3,254,233 Patented May 31, 1966 the pulsereshapers have become important problems. As regards the waveformdistortion in the delay line,-the relationship between the delay time.and the time of rise and fall is that as the delay time increases thetime of rise and fall also increases as illustrated in FIG. 2, that is,the rise and fall time is approximately proportional to the delay time.This means that for a given delay time the waveform distortion growsheavier as the speed of pulse signal increases and that the longer thedelay time required, the more extended delay line is required and withthis the waveform distortion of the delayed output signal grows heavier.This forms a critical problem particularly in case the device isoperated at higher speeds.

In order to minimize such waveform distortion deriving from the delayline, a divided system has been proposed in which the delay line isdivided into a number of stages, De De De with pulse reshapers S S Sinterposed between the adjacent stages, as illustrated in FIG. 3. In thedivided type register, the delay time required with each of the delaylines D2 De De will be l/n times that of the delay line De in theregister of FIG. 1 for the same time delay requirement. This means thatthe degree of wave distortion at each stage is also reduced to l/n.Also, it will be understood that the cycle time variable range of clockpulses, keeping the systemin correct operation, is increased n-fold.Assuming that AT represents the allowable time deviation in timeposition of the clock'pulse as delayed a predetermined time by theundivided delay line and the deviation of the clock pulse for the samecycle time at each of the n stages in the divided register will berepresented by A deviation of AT will take place at each stage only whenthe variation in the cycle time is increased n-fold. Thus, by doingthis, the allowable margin for the cycle time variation may beincreased. In this case, however, since each stage includes a pulsereshaper, the distortion due to the variation in the operating voltagelevel of such pulse reshaper (generally an increase or decrease of thepulse width) will be accumulated stage by stage to appear in the outputas such. This means that the variation in the operating voltage level ofa pulse reshaper forms a critical problem with the divided system thoughit has little influence when a single-stage delay line is used. Furtherconsideration will be made below in this regard.

FIG. 4 illustrates the arrangement of each of the pulse reshapers usedin FIG. 3. The pulse reshaper shown in cludes current switchingamplifiers A A and a re-timing AND gate D. The amplifiers A A are eachof the socalled differential type essentially including two transis-'tors T and T as shown in FIG. 5. In operation of this circuit, acomparison is made between the reference voltage V impressed to the baseof transistor T and the base voltage V, of transistor T in the mannerwell' known in the art; As long as no input pulse is impressed to thebase of transistor T V is greater than V, Under this condition, nooutput appears at the positive output terminal out but a pulse signal isproduced at the negative output terminal out On the other hand, when aninput pulse arrives at the base of transistor T to obtain a state V V apulse signal will appear at terminal out but not out A voltage source Vis provided to set up a pedestal level V.,, which corresponds to V, innormal state, i.e., when V V,,.

Referring again to FIG. 4, the conventional current switching amplifieruses only the positive output terminal,

therefore, input pulse 2 entering the input terminal of nized reshapedoutput pulse e at the positive output terminal of the amplifier A Withthis circuit, variations in the reference voltage V in eachcurrent-switching amplifier and in the source V for setting up pedestallevel V are called in question. Referring next to FIG. 6, whichillustrates waveforms of (a) input pulse e, (b) positive output ofamplifier A and positive output of amplifier A As long as the referencevoltage is held at its predetermined level, the output of amplifier Awill be a pulse 2 (indicated by a thick line in FIG. 6, (b)) which risesat time t when input pulse e exceeds the V level and falls at time twhen it is reduced below the V level. Assume that the output pulse e isapplied intact to the second amplifier A as its input. When thereference level V has also its predetermined value, the positive levelor output e takes the form of a pulse e having the waveform (c) in FIG.6, which rises at t when e exceeds the V level and falls at when 2decreases below V level. If the V level of both the amplifiers A and Ais raised to V the output pulse of amplifier A will be as indicated at ein FIG. 6, (b), for the same input signal e. The output pulse e isreduced in width compared with the normally obtained pulse e as will beobserved in-the figure. Such pulse of reduced Width is sent to thesecond amplifier A which has now reference level V as distinct fromprevious level V and the output of which takes the form of a pulse e (in(c) of FIG. 6), which has a width narrower than that of normal output eIn this case of two-stage amplification, the rate of reduction in pulsewidth at stage A when the reference level V is varied to V is twice thatat stage A Similarly, when the reference level V is reduced to V theoutput pulses obtained at respective stages A and A are extended inwidth as indicated at e in FIG. 6, (b) and e in FIG. 6, (c),respectively. In this case, the rate of extension in pulse width atstage A is also twice that at stage A As described above, any variationin the reference voltage V (or in source voltage V for setting up Vsince the variation in V is entirely relative to the variation in Vcauses reduction or extension in width of the reshaped output pulse.Therefore, in the divided system including at each stage such a pulsereshaper, the reshaped pulse output of which is reduced or extended inWidth with variation in the operating level, a pulse reduced or extendedin width at the first stage is again reduced or extended at the secondstage. Such reduction or extension is repeated at the following stagesto obtain at the output or final stage a pulse which has an extremelynarrow or wide width compared with that of the input pulse entering thedelay line register, since the reduction or extension in width isaccumulated stage by stage. In case the pulse width is extended stage bystage, there is a danger that it may overlap the clock pulse of the nextcycle. This necessitates reduction in the clock pulse cycle time when itis desired to raise the speed of operation. However, it is noted thatsuch reduction is subject to heavy limitations and causes markedreduction in the reduced allowable margin of the clock pulse.Particularly, in case the pulse width is reduced, the allowable marginof the clock pulse is narrowed by the fact that the width of the logicalproduct pulse output of the re-timing AND gate is also reduced.

In the foregoing description it has been assumed that reference voltageV varies. However, the operation will be the same even if source voltageV is assumed to vary since the variation of V and that of V are entirelyrelative to each other, as pointed out hereinbefore. The fact that suchvariation of V is efiective to reduce or extend the pulse width in thesame manner as described, makes it necessary to narrow the variablerange of voltage V to an extreme extent to obtain a correct operationagainst the cycle time variation AT, but such limiting range of voltageV is extraordinarily difiicult in practical use.

Description will next be made with reference to FIG. 8, whichillustrates one constructional example of a circuit arrangement largelysimilar to the reshaping circuit of FIG. 4 and embodying the presentinvention. This circuit includes current-switching amplifiers A Asimilar to those in FIG. 4 and a re-timing gate D interposed between thetwo amplifiers.

In operation of this circuit, input signal e is reshaped and amplifiedby amplifier A the negative output -e of which is directed to there-timing gate D through terminal out (FIG. 5). The output of there-timing gate, being synchronized therein with the negative clock pulsee is again reshaped and amplified in amplifier A from the negativeoutput terminal of which a desired reshaped output e is obtained.

With this arrangement, it is assumed that the source voltage V (or thereference level V of each of the amplifiers A and A varies as describedhereinbefore in connection with the circuit of FIG. 4. The output ofeach amplifier will then have the waveform shown in FIG. 7. FIG. 7illustrates an input pulse in (a), which is similar to one shown in FIG.6, (a),- the negative output signal Olf amplifier A for such input pulsein (b), and the negative output signal of amplifier A in (c), when theoutput of amplifier A is led intact to enter the a mplifier A As long asreference voltage V or source voltage V has a normal value, the negativeoutput signal from A is as indicated at e in FIG. 7, (b) and thenegative output of A is as indicated at E in FIG. 7, (c) and identicalwith e shown in FIG. 6, (c). In case reference voltage V is varied to Vtherespective negative outputs of the amplifiers A and A will havewaveforms e and E respectively, shown in FIG. 7, (b) and (c). Asobserved, the negative output E has a pulse width extended relative tothat of the corresponding output 2 shown in FIG. 6, (c) and issubstantially equal to E (=e Contrariwise, in case V is reduced to V therespective negative outputs of A and A will have waveforms e and Erespectively shown in FIG. 7, (b) and (c). The negative output E of Ahas a width reduced relative to that of the corresponding output 2 shownin FIG. 6, (c) and substantially equal to E In this circuit arrangementembodying the present invention, when the source voltage V (or referencevoltage V supplied to amplifiers A and that supplied to amplifier A varyas described above, i.e., at the same time and in the same direction, anegative output is led from amplifier A and is again negated byamplifier A The pulse signal once extended (or reduced) in A is thusreduced (or extended) in A for proper correction. Accordingly, when apulse reshaping circuit as illustrated in FIG, 8 is used in FIG. 3 foreach of pulse reshapers S S S S,, S an extraordinarily stable circuitoperation can be expected compared with the case in which pulsereshapers each as shown in FIG. 4 are employed, since any variation inpulse width at each stage occurring due to variation in the operatingvoltage level is effectively corrected or compensated at the followingstage or stages. The reference cycle time of clock pulses is usuallykept fixed by a stable crystal oscillator of known construction. Inpractical use, then, the time deviation of cycle time is nearly zero. Inthis case, AT is equal to the time delay variation in the delay line andthe pulse reshaper. In other words, the arrangement of the presentinvention gives to the source voltage V a much wider variable range thanthat obtained with the circuit of FIG. 4.

FIG. 9 represents the results of experiments conducted with divided typedelay line registers of 12:2 as shown in FIG. 3 for comparison betweenthose employing conventional pulse reshapers as shown in FIG. 4 andthose employing the circuit of FIG. 8 embodying the present invention.In FIG. 9, the abscissa gives the cycle time deviation AT from thereference T in percentage, and the ordinate gives the voltage V Theregion I is a range of correct operation obtained with conventionalpulse reshapers and the region H is that obtained with pulse reshapersof the present invention. As is clearly observed, region II is muchwider than region I.

It will be understood that the same correcting efiect can be obtainedwith the above embodiment even when arranged so that the input pulse eentering the first pulse reshaper S is just inverted therein and theinverted output of the reshaper S is transmitted through the delay lineD2 to the next pulse reshaper S to be again inverted therein, suchinversion being further repeated in the succeeding stages including thefinal one.

Though some forms of delay line register have been described and shownherein, it is to be understood that the reshaping method of the presentinvention is not to be limited to such registers but may also beadvantageously applied to other various pulse transmission circuits. Insuch applications, synchronization may not always he required, and thelogical gating circuit can thus be eliminated from between amplifiers Aand A In some cases, .a delay line or other circuit may be interposedbetween amplifiers A and A as desired. There is no intention ofexcluding such equivalents of the invention described or the portionsthereof as fall within the purview of the claims.

What is claimed is:

1. A delay line register comprising a delay line divided into aplurality of delay line units,.and delay combinations comprisingdifierential amplifiers respectively connected to input and output sidesof each of said delay line units, said delay combinations beingconnected in cascade for transmitting an inverted output of each of saidamplifiers to a following amplifier.

2. A delay line register comprising a plurality of delay linecombinations connected in series each including a 4 delay line unit anddifferential amplifier means connected to input and output sides of saiddelay line unit, adjacent difierential amplifier means being connectedto one another between respective combinations so as to produceinversion of a transferred waveform between successive amplifier means.

3. A delay line register comprising an alternate arrangement ofdifferential amplifier means and delay line units connected in seriesrelationship, said differential amplifier means consisting of a pair ofdifferential amplifiers each having an input and an output and beingconnected in series with gate means connected between that output of oneof said difierential amplifiers providing an inverted waveform and theinput of the other differential amplifier that output of the otherdifferential amplifier providing an inverted waveform being connected toa following delay line unit.

4. A delay line register comprising an alternate series arrangement ofdiiferential amplifier means and fractional delay line unitsinterconnected thereby, each differential amplifier means including aninput and an output and producing at least one inversion within saidamplifier means of a waveform transferred between said input and saidoutput.

5. A delay line register comprising an alternate series arrangement ofdifferential amplifier means and fractional delay line unitsinterconnected thereby, said differential amplifier means including apair of series connected differential amplifiers, each producing aninversion of a transferred waveform between successive amplifiers.

References Cited by the Examiner UNITED STATES PATENTS 2,647,998 8/ 1953Paxson 328- X 2,710,944 6/1955 Banger-t 330-57 X 2,875,336 2/1959Williams 328-66 X 3,080,531 3/1963 Koppel et a1. 33069 3,103,635 9/1963Campbell et a1. 33()16 X ARTHUR GAUSS, Primary Examiner.

1. A DELAY LINER REGISTER COMPRISING A DELAY LINE DIVEDED INTO APLURALITY OF DELAY LINE UNITS, AND DELAY COMBINATIONS COMPRISINGDIFFERENTIAL AMPLIFIERS RESPECTIVELY CONNECTED TO INPUT AND OUTPUT SIDESOF EACH OF SAID DELAY LINE UNITS, SAID DELAY COMBINATIONS BEINGCONNECTED IN CASCADE FOR TRANSMITTING AN INVERTED OUTPUT OF EACH OF SAIDAMPLIFIERS TO A FOLLOWING AMPLIFIER.